A low power block-matching analog motion estimation processor

This paper presents an analog motion estimation processor utilizing the full-search block-matching algorithm for portable video applications. The system features digital I/O and a low power, area efficient analog computation core. The proof-of-concept processor was fabricated in 0.8/spl mu/m CMOS occupying 0.63 mm/sup 2/, and operates on 4-by-4 pixel blocks and a search window of 8-by-8 pixels. Its architecture is however readily scalable to larger pixel blocks and more advanced technologies. Measured results for QCIF video sequences show excellent PSNR performance. A comparison with all-digital equivalents is presented, showing the superiority of the analog approach in all relevant metrics.