Hierarchical instruction encoding for VLIW digital signal processors

VLIW-based architectures are very popular in high-performance DSPs, for their relatively simpler implementations and more predictable execution times. But they need more program memory because of (1) the fixed-length instruction encoding, (2) NOP insertion due to limited parallelism, (3) repetitive codes for loop unrolling. The paper describes a novel hierarchical instruction encoding that addresses these three problems in order to improve the VLIW code density. In simulations, the proposed encoding scheme saves 61.4-66.9% code sizes in highly parallel DSP kernels, and more savings can be expected for general programs. Besides, a simple decoding architecture is proposed and has been integrated into a 4-way VLIW DSP. The prototype is implemented in 0.18 /spl mu/m CMOS technology with its operating frequency at 208 MHz.