A 5V charge pump in a standard 1.8-V 0.18-/spl mu/m CMOS process

A new high voltage tolerant charge pump structure, designed with a standard low voltage CMOS process, is presented. This fully integrated charge pump design uses a symmetrical structure and can be scaled to achieve higher voltages up to a certain limit. The design is based on a standard 1.8-V 0.18-/spl mu/m CMOS process without the high voltage option. Simulation result shows an output voltage of 5.12 V with a 250 k/spl Omega/ load and an operating frequency of 2.5 MHz. The efficiency of the circuit is 77% and satisfies typical voltage stress related reliability requirements for low voltage CMOS devices.