Parameter extraction for on-chip interconnects by double-image Green's function method combined with hierarchical algorithm

A novel double-image Green's function approach combined with the hierarchical algorithm is proposed to compute the frequency-dependent capacitance and conductance for the on-chip transmission lines and interconnects embedded in multiple SiO/sub 2/ layers of the general CMOS process. The effect of a protective layer and lossy silicon substrate layer of the CMOS process are considered in the four-layer structure deduced by the equivalent dielectric-constant approach whose adaptability is further proven in this paper. This double-image Green's function approach is fast convergent with the increasing order of reflections and transmissions, which is further accelerated by the hierarchical algorithm for computation of the Green's function rapidly. Moreover, the proposed method avoids the computation of bound charges on the dielectric interfaces. The frequency-dependent capacitance and conductance gained from the proposed method are shown to be in good agreement with the data obtained by other relevant methods.