A scaled CMOS-compatible smart power IC technology

An integrated VDMOS-based PIC process was developed to increase the cost effectiveness and performance of 60 V high current circuits. Compact 60 V CMOS elements and a 140 m Omega -mm/sup 2/ VDMOS were integrated into a 3 mu m CMOS process using only one additional mask. This increased level of integration allowed the use of a cell-based ASPIC (application-specific power IC) methodology as an attractive alternative to conventional full-custom approaches. This was demonstrated in the development of a 10 A intelligent power switch for automotive applications.<
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