Design and optimization of a hot-carrier resistant high-voltage nMOS transistor

The hot-carrier degradation behavior of a class of high-voltage n-channel drift MOS transistors is experimentally investigated as a function of the geometrical (layout) parameters of the devices. The design restrictions, imposed by reliability requirements, are described as a subset of the space of the geometrical parameters (safe volume) which guarantees a safe hot-carrier operation. The optimization of the specific drain/source on-state resistance of the devices within the safe volume is discussed.