Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment

Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. In this paper, we propose new leakage current reduction methods in standby mode. First, we propose a combined approach of sleep-state assignment and threshold voltage (V/sub t/) assignment in a dual-V/sub t/ process for subthreshold leakage (I/sub sub/) reduction. Second, for the minimization of gate oxide leakage current (I/sub gate/) which has become comparable to I/sub sub/ in 90-nm technologies, we extend the above method to a combined sleep-state, V/sub t/ and gate oxide thickness (T/sub ox/) assignments approach in a dual-V/sub t/ and dual-T/sub ox/ process to minimize both I/sub sub/ and I/sub gate/. By combining V/sub t/ or V/sub t//T/sub ox/ assignment with sleep-state assignment, leakage current can be dramatically reduced since the circuit is in a known state in standby mode and only certain transistors are responsible for leakage current and need to be considered for high-V/sub t/ or thick-T/sub ox/ assignment. A significant improvement in the leakage/performance tradeoff is therefore achievable using such combined methods. We formulate the optimization problem for simultaneous state/V/sub t/ and state/V/sub t//T/sub ox/ assignments under delay constraints and propose both an exact method for its optimal solution as well as two practical heuristics with reasonable run time. We implemented and tested the proposed methods on a set of synthesized benchmark circuits and show substantial leakage current reduction compared to the previous approaches using only state assignment or V/sub t/ assignment alone.