Fine-grain system architectures for systolic emulation of neural algorithms

A systolic approach is described that is well suited to solve the neural net interconnection problem and cope with neural application areas like vision or speech. The proposed neuro-emulator concept is sizeable to the application domain in terms of processing power, memory and flexibility, and it is designed for throughput rates that enable the user to access real-world applications in reasonable time. At the chip site, throughput rates on the order of 10/sup 3/ MC/s (1 connection=16 b) are to be expected with 0.8 mu m CMOS technology. Two-dimensional systolic extension at the board level will allow the processing of about 10/sup 5/ MC/s.<
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