New extraction method for gate bias dependent series resistance in nanometric double gate transistors

Double gate type transistors are needed for the ultimate integration on silicon, and thus extraction techniques have to be adapted. In this paper, the influence of the series resistance on the extrinsic mobility reduction parameters is analysed, in the case of a resistance varying with the gate bias. It is evidenced that both the low field and high field parameters are impacted. Then, a new approach is proposed for the extraction of the series resistance variation with the gate voltage, and applied to the analysis of gate-all-around transistors series resistance, with doped and undoped body.