Multilayer metallization for LSI

Recent advances in the manufacture of complex bipolar integrated circuits have led to a variety of techniques for metal interconnection on the chip. As the need for more and more devices has increased chip size, the problem of random defects has become catastrophic. Functional yields are often seen to drastically decrease or even vanish with attempts to fabricate very large bipolar parts. Since the major factor determining die size is the metal interconnect size and spacing, one way to conserve "real estate" while achieving highly complex circuits is to employ more than a single layer of interconnection metal. At present both double- and triple-layer schemes are being used. These multilayer metallizations, while solving the problem of chip defects, are not without serious drawbacks of their own. These problems are discussed. The Motorola multilayer systems considered are all aluminum based; i.e., pure aluminum or lightly doped aluminum. Although other metals are being experimented with, aluminum systems make up nearly all of the commercially available ICs at this time. In general, these metal layers are insulated from one another by a deposited dielectric, usually SiO
2
. The most prominent yield limiting problems are discussed. These include coverage of both metal edges and oxide steps with additional metal and/or another layer of oxide. Processing parameters such as profiles, thickness, temperature, composition, etc., that influence coverage are discussed as well as innovations for improving less-than-desirable results.