Implementation of a 4 /spl times/ 4 switch with passive interconnects

We designed and fabricated a 4 /spl times/ 4 switch in which all interconnections were implemented using passive transmission lines (PTLs). The switch consisted of four identical 2 /spl times/ 2 switches connected using PTLs. The 2 /spl times/ 2 switch was designed using gate-to-gate passive interconnections. Using the on-chip testing method, we demonstrated 40-GHz operation of the 4 /spl times/ 4 switch. To verify the effectiveness of passive interconnection, we compared the 4 /spl times/ 4 switch with an identical switch that was designed using Josephson transmission lines (JTLs) for interconnections. The comparison showed that the PTL-version 4 /spl times/ 4 switch had 50% fewer junctions and required 55% less powering current. The latency and the largest jitter in the PTL-version 4 /spl times/ 4 switch were estimated to be 36% and 61%, respectively, of those of the JTL version.