A CMOS 10-bit low-power pipelined A/D converter

An experimental low-voltage low-power 10-bit pipelined analog-to-digital converter for video-rate applications is presented in this paper. The 1.5b/stage architecture with digital correction is adopted in this pipelined ADC. It consists of 9 stages in which only 19 comparators and 9 low power operational amplifiers are needed. Fully-differential structure is used to increase the noise immunity and reduce 2nd order harmonic distortion. The ADC achieves a signal-to-noise-and-distortion of 53dB for whole-chip simulation with 2MHz input sampled at 20Msamples/s, consuming 28.7mW. It is implemented in 0.6/spl mu/m CMOS technology with a core area of 1.55mm/sup 2/.