A broadcast/reduce architecture for high-speed data compression

The author presents a parallel architecture for high-speed data compression based on textual substitution using a sliding window. The architecture combines a systolic array with trees for data broadcast and reduction. Compression involves two steps. First, a match generator computes in parallel the maximal matches available at each position of the input. The generator uses a systolic array to hold the dictionary, a pipelined broadcast tree to deliver each input character simultaneously to every array cell, and a reduction tree to identify the largest available match each cycle. From this information a second process selects a match sequence exactly covering the input. Decoding mirrors encoding. The tree interconnect provides through-delay proportional to the log of the dictionary size, and pipelining reduces the effective per-character processing time to a single system cycle. A system data rate of 300 Mbit/sec is easily attainable. The author discusses layout issues arising from the tree interconnect.<
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