A complete BIST scheme for ADC linearity testing

In this paper, we presented algorithms for testing gain error, offset error, differential nonlinearity (DNL) and integral nonlinearity (INL) of analog-to-digital converters (ADC), and proposed an easily integrated built-in self-test (BIST) scheme on chip, which has been designed using Chartered 0.35 /spl mu/m technology. The experimental results show that the proposed BIST scheme has low area overhead, low test cost and high test accuracy.