Pseudorandom scan BIST using improved test point insertion techniques

This paper attempts to present a new design-for-testability (DFT) method which implements an improved test point insertion strategy on pseudorandom scan BIST. The testability of a circuit is affected greatly by the reconvergent fan-outs and their branches. We first introduce a testability measure based on analysis of conditional probability. It considers the reconvergent fan-outs' influence on testability and can be applied to select the signal lines where the test points should be inserted. Then, we present a new test point structure and a new test point insertion technique which can cut down the timing delay and area overhead of traditional ones. The proposed DFT technique has been used in pseudorandom scan BIST and experimental results proved its effectiveness on improving the testability and reducing the testing cost.