A novel Monte-Carlo method for FPGA architecture research

A new Monte-Carlo-based approach is proposed for FPGA architecture research. Uniform open faults are randomly produced in the routing resource; and then interconnections are routed around obstacles. It does not depend on CAD algorithms and benchmark circuits. An example of switch block topology evaluation shows one can capture the same conclusion as that of CAD methods and shorten run-time from 15 hours to 15 minutes.