Novel VLSI architecture of 2-D DWT/IDWT for JPEG2000 based on diagonal storage

An efficient VLSI architecture of 2D DWT/IDWT for JPEG2000 is proposed. In this architecture, the memory consists of eight dual port SRAM memories where image data is diagonally stored, and a 1D DWT based lifting scheme is implemented using pipeline processing techniques. The 1D DWT core can process 4 sample data in a clock cycle. According to different requirement, this architecture can be implemented with or without an external buffer. Simulation results show that this design is able to perform a 3-level decomposition for a 512/spl times/512 grayscale image within 13.3 ms (with an external buffer), or 16.6 ms (without an external buffer) when running at 20 MHz.