Unique capacitance phenomenon of a 100nm double-gate FD SOI NMOS device with n/sup +//p/sup +/ poly top/bottom gate

This paper reports the unique capacitance phenomenon of 100nm double-gate (DG) fully-depleted (FD) SOI NMOS device with the n/sup +//p/sup +/ poly top/bottom gate. Based on the 2D simulation result, the gate-drain/source capacitance (C/sub GD//C/sub GS/) of the device shows a sudden fall at the gate voltage of 0.5V due to the existence of the hole accumulation/depletion in the bottom channel controlled by the p/sup +/ bottom gate.