Design and hardware implementation of digital channel selection processor for radio receiver

This paper presents a low-power design and an area-efficient FPGA implementation of digital channel selection filtering processor for radio receiver. For an homodyne wide-band RF receiver and sigma-delta modulator, two filtering cascade structures composed of 5 stages comb filter, FIR half-band filter and selector filter are compared. Design flow of hardware architecture is presented through digital data format representation and topology of digital operators. Experimental results are given to evaluate performances and complexity of designed FPGA-based implementation.