Hierarchical systolic array design for full-search block matching motion estimation

We present here a hierarchical design methodology for the full-search block matching motion estimation. The methodology takes into account input data timing specifications and well as buffering requirements. System performance is manipulated by selecting some of the algorithm variables for pipelining or broadcasting. The design strategy also allows modifying time and hardware complexities at each level of the hierarchy in order to match system speed and hardware complexity to design specifications.