Glitch elimination by gate freezing, gate sizing and buffer insertion for low power optimization circuit

One of the major factors contributing to the power dissipation in CMOS digital circuits is the switching activity. Many of such switching activities include spurious pulses, called glitches. In this paper, we propose a new method of glitch reduction by gate freezing, gate sizing, and buffer insertion. The proposed method unifies gate freezing, gate sizing, and buffer insertion into a single optimization process to maximize the glitch reduction. The effectiveness of our method is verified experimentally using LGSynth91 benchmark circuits with a 0.5/sup um/ standard cell library. Our optimization method reduces glitches by 65.64% and the power by 31.03% on average.