RSA encryption/decryption in wireless networks using an efficient high speed multiplier

This paper proposes a faster RSA encryption/decryption circuit utilizing a high speed multiplier architecture. The proposed two's complement N XN bit multiplier architecture is based on two concepts: the partial products can be generated in parallel with a delay of d; and thereafter the addition can be reduced to log/sub 2/N steps. The most significant aspect of the proposed RSA hardware is that any future proposed efficient adder can be implemented in the proposed multiplier, without changing the original hardware architecture, thereby improving its efficiency to a great extent. The coding of the RSA is done in Verilog HDL and the FPGA synthesis is done using Xilinx libraries. The result shows that the RSA hardware implemented using the proposed architecture is faster than RSA hardware implemented using the traditional multiplication algorithm.