A multi-standard video coding accelerator based on a vector architecture

We discuss the architecture definition and microarchitecture of a multi-standard, parametric vector accelerator for block-based video coding. Our target coding algorithms were the MPEG-2 TM5, MPEG-4 (XViD) and STM's proprietary H.264 implementation. We fully vectorized the MPEG-2 and MPEG-4 coders and partially vectorized the H.264 encoder. In the proprietary H.264 case, we targeted the inner loop of the motion estimation function. Our preliminary results demonstrate a significant complexity reduction of the order of 65%, 70% and 16% for MPEG-2, MPEG-4 and H.264 respectively. In the latter case the complexity of the inner loop of motion estimation has been reduced by 79% compared to the scalar case.