A comprehensive analysis of NFET degradation due to off-state stress

This work gives a comprehensive insight into the performance degradation of NFETs after off-state or non-conducting stress (NCS), respectively (V/sub ds/=V/sub DD/, V/sub ds/=0 V). The investigated off-state stress is highly product relevant for DRAM as well as for logic. During the stress, an increase of the threshold voltage and therefore a decrease of the saturation current of the transistors is observed. The revealed parameter shift is due to the creation of electron traps. The electron traps are generated by holes which originate from impact ionization of the sub V/sub th/ current. The time dependence of the degradation obeys a power law with a slope of /spl sim/0.5. Whereas the parameter drift of the transistor is accelerated linearly with the drain voltage, at least for high stress voltages.