Pipelined Function Evaluation on FPGAs

This paper presents an approach to parameterizing pipelined designs for differentiable function evaluation using lookup tables, adders and multipliers. Trade-offs involved in implementing the lookup table as a full table or as bipartite tables are discussed. In case of implementations with a lookup table and a multiplier, equations estimating approximation errors and rounding errors can be used to parameterize the hardware unit. The method is implemented as part of the PAM-Blox module generation environment. An example shows that our approach produces competitive designs with data widths up to 20 bits when compared with shift-and-add based CORDIC units; it can be used for larger data widths when evaluating functions not supported by CORDIC.