Evaluation of Reconfigurable Cache Module Architecture

This paper presents the details of a superscalar microarchitecture to support reconfigurable cache modules. A reconfigurable cache module can be used either for caching or for computing. The reconfiguration latencies dictate that these modules be used for computations involving multiple data items. We evaluate this microarchitecture for a variety of multimedia computation kernels through simulations. The out-of-order superscalar simulator from the publicly available microarchitecture simulation toolset SimpleScalar was modified to incorporate the reconfigurable cache modules. The simulation results indicate a reduction of 10%-85% in execution time for multi-media applications such as adpcm and mpeg.