A highly manufacturable low-k ALD-SiBN process for 60nm NAND flash devices and beyond

For the first time, low-k dielectric ALD-SiBN (atomic layer deposition) is successfully developed and applied on poly-Si/WSix gate as a spacer for reduction of parasitic capacitance between the cells. ALD-SiBN deposition is performed at 630/spl deg/C using dichlorosilane (SiH/sub 2/Cl/sub 2/-DCS), boron-trichloride (BCl/sub 3/) and ammonia (NH/sub 3/) as precursors. Compared with the conventional silicon nitride, ALD-SiBN exhibits similar film properties at lower dielectric constant. ALD-SiBN layer is deposited on poly-Si/WSix stack gate in 90nm NAND flash device. A significant reduction (>15%) of the floating-gate coupling voltage is achieved by employing SiBN compared with SiN spacer. In addition, excellent data retention characteristics (@HTS) is identified by applying low-k dielectric SiBN layer as a spacer on 90nm NAND flash device.