A systematic study of trade-offs in engineering a locally strained pMOSFET

We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman spectroscopy (/spl mu/RS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.