ESD and latch-up reliability for nanometer CMOS technologies

Considerable research during the 80's and 90's laid the foundation for a deeper understanding of the ESD high current device physics and the subsequent protection design techniques required to achieve ESD reliability for numerous applications (Amerasekera and Duvvury, 2001; Dabral and Maloney,1998). Indeed, at every node a different parameter has had the most influencing effect, especially on ESD. This paper will review the recent trends as the industry moves towards nanometer technologies. New circuit applications are also discussed to introduce the upcoming critical issues for ESD and LU design.