Pragmatic design of nanoscale multi-gate CMOS

Three-dimensional numerical device simulations are done to gain physical insights on multi-gate FinFETs, which portend the infeasibility of nanoscale triple-gate CMOS, and process/physics-based device/circuit simulations are done to check the concept of pragmatic nanoscale double-gate CMOS design, showing encouraging performance projections near the end of the SIA 2003 ITRS (2003).