3D GOI CMOSFETs with novel IrO/sub 2/(Hf) dual gates and high-k dielectric on 1P6M-0.18 /spl mu/m-CMOS

For the first time, we demonstrate 3D integration of self-aligned IrO/sub 2/(Hf)/LaAlO/sub 3//GOI CMOSFETs above 0.18 /spl mu/m Si CMOSFETs. At EOT=1.4nm, the novel IrO/sub 2/(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO/sub 3//Si devices have high electron and hole mobilities of 203 and 67 cm/sup 2//Vs. On the 3D structure the LaAlO/sub 3// GOI shows even higher 389 and 234 cm/sup 2//Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.