Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high-/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm (due to: (i) elimination of poly depletion effect, /spl sim/ 0.5 nm, and (ii) the high mobility of HfSi/sub x/O/sub y/). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)/spl sim/ -0.4 V and Vt(NFET) /spl sim/ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V/sub t/ stability) was found in the case of NiSi/ HfSi/sub x/O/sub y/ compared to the same gate electrode with HfO/sub 2/ dielectric.