VLSI architecture for HMM-based speech recognition systems and its verification platform

This work presents VLSI architecture in HMM-based speech recognition for high-speed operation and its verification platform to test various tasks on recognition systems. The proposed architecture effectively utilizes independent computations on the HMM structure. It can reduce processing time and/or extend the word vocabulary considerably. We designed a complete recognizer, including speech analysis and noise robustness parts, and developed a FPGA platform and a computer-aided design tool that generates source codes and testing data. The recognizer provides 35.7 /spl mu/s/word in response time for word recognition tasks on a 0.18 /spl mu/m CMOS technology and the FPGA platform enables real-time recognition experiments under various conditions.