Realization of a systematic bit-wise decomposition metric

In this paper, a realization structure for our previously proposed systematic recursive formula for bitwise decomposition of M-ary symbol metric is proposed, which can be applied to reduce the memory space and processing latency of a system where the information sequence is binary-coded and interleaved before M-ary modulated. Different from conventional structure where de-interleaver and decoder are separate circuits, our structure de-interleaves and decodes at the same time.