Automatic protocol translation and template based interface synthesis for IP reuse in SoC

Reuse of intellectual property (IP) is crucial in SoC design. The discrepancies in interface logic and communication/bus protocols among IPs, however, remain as the main obstacle in system integration. We examine the interface logic generation problem and propose a novel scheme to automate the process. The scheme consists of an automatic communication/bus protocol translation and a template based interface logic/bus wrapper generation. Real case test bench, e.g. AHB in AMBA v.s. BVCI in VCI was applied to verify the correctness and the efficiency of the generated interface. The design is also implemented in FPGA and incurred interface circuitry overhead is small.