Test volume reduction via flip-flop compatibility analysis for balanced parallel scan

Test generation for scan-based test of sequential circuits is typically performed by generating tests for the embedded combinational logic (ECL) and translating these into scan test vectors. However, the serial nature of scan-based test incurs significant overhead in terms of test application time. To reduce the test data volume, in this paper we propose a new algorithm for compatibility analysis of the circuit flip flops. This algorithm, when applied to parallel-scan methods such as the Illinois Scan Architecture (ILS), results in shorter and more balanced scan chains. It also eliminates the need to apply test vectors in serial mode. As a result, an average reduction of 1.4/spl times/ and a maximum reduction of 1.7/spl times/ in test data volume was obtained for the ISCAS89 benchmarks, over current versions of ILS.