A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the on state, an inversion layer is induced by the subgate as a drain so that the on current is still high and the poly-Si region under the subgate behaves as an offset, reducing the off-state leakage current during the off-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum off-state leakage current of the new TFT is decreased from 1.4/spl times/10/sup -10/ to 1.3/spl times/10/sup -11/ without sacrifice of the on current. In addition, the on-off current ratio is significantly improved.