A crosstalk tolerant latch circuit design

A D-latch sequential circuit design is presented that exhibits an elevated degree of tolerance to common and differential mode noise in the clock lines. The circuit tolerates noise voltages in the clock signals in the range of or even higher than +or-V/sub dd/, becoming under specific conditions a dynamic latch preserving the system from the propagation of unknown quality information. The circuit and the design rules presented are oriented to VLSI circuits design in which crosstalk perturbations may be foreseen.<
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