Power supply noise modeling and correlation for a 3.2 GHz bidirectional differential memory bus

This work describes the modeling of power supply noise in a high-bandwidth XDR/spl trade/ DRAM memory system and the correlation with measurement results in time domain while the system is operating. A supply network model is presented that allows prediction of worst-case supply noise outside as well as inside the device packages. Comparison of simulation results with measurements outside the package show excellent correlation, verifying the modeling approach.