High-end server system partitioning for cost reduction

In this work finite dimension integer programming for 2-core and 3-core chip designs is used to define the optimum number of processors in a SMP node (symmetric multi-processing) from the point of view of minimizing the number of the chips that cannot be used in the system even if they have functionally good PU cores on them. In effect the trade-offs between the PU cores on a chip, the number of PU on an SMP node, and the cost of the chip are studied. It is asserted that to the first order the cost of the chips is proportional to the scrap of chips with good cores on them that cannot be used in the implementation of the SMP nodes. The model shows that an optimized SMP offering can be defined so that the total chip cost of high-end server system can be reduced. This desired cost reduction limits the SMP node size for a given processor chip yield. It is shown that as the chip yields are improved, the SMP node size that can be profitably implemented can also be increased.