IEC/IEEE International Standard - Behavioral Languages - Part 5: Standard VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification

IThe VITAL (VHDL Initiative Towards ASIC Libraries) ASIC Modeling Specification is defined in this standard. This modeling specification defines a methodology which promotes the development of highly accurate, efficient simulation models for ASIC (Application-Specific Integrated Circuit) components in VHDL.