A fast algorithm and hardware implementation for rate-distortion optimization in JPEG2000

A fast algorithm for T/sub 2/ encoder in JPEG2000 suitable for hardware implementation is presented in this paper, based on the elaborate analysis of a rate-distortion optimization algorithm. By reducing calculative complexity, the difficulty of hardware implementation for the T/sub 2/ encoder is reduced, and the parallelizability of the JPEG2000 hardware system is enhanced. The experimental results show that the final code stream is in accordance with the standard format of JPEG2000 and reconstructed image quality decreases little. The system has been implemented on FPGA.