Characteristics of an integrated programmable interconnect array for analog circuits applications

This paper unveils the results of characterization of a programmable interconnect array, which has been designed and fabricated in 0.6/spl mu/m/5V standard CMOS. The developed interconnect array is organized in a 4-row by 4-column fashion, thus comprising 16 nodes. Each node is composed of six N-channel MOS switches laid out in such way that two distinct paths can share the same node with or without crossing over. Exhaustive measurements have shown that the developed array fulfills the main requirements for interconnecting analog blocks in field-programmable applications. The impedance between two adjacent nodes is predominantly resistive up to 3MHz, measuring circa 500/spl Omega/. Lower and upper level limits for voltage signals propagating in the longest path are -2.5V and +0.7 V, respectively.