A scalable and pipelined FPGA implementation of an OC192 WF scheduler

We propose an FPGA implementation of a multi protocol weighted fair (WF) queuing algorithm able to handle variable length packets targeted for POS interfaces and ideal for the design of hybrid IP/ATM switches. Our contributions are two folds: first, we have combined the Highest Value First scheme and the Round Robin scheme into a single pipelined design able to schedule traffic for 4 channels in parallel. Second, we showed how to build higher order WF queuing system without decreasing the overall performance of our scheduler. As a result, our scheduler is general enough to accommodate ATM (UTOPIA L3/L4) , POS/PL3 (OC48) as well as POS/PL4 (OC192) interfaces.