An approach to realize time-sharing of flip-flops in time-multiplexed FPGAs

This work introduces a new approach to realize timesharing of flip-flops in time-multiplexed FPGAs. In order to implement large circuits in time-multiplexed FPGAs, it is important that flip-flops, as well as combinational logics, must be time-shared efficiently. To handle sequential circuits, previous works either required large amount of communication between sub-circuits or caused storage overhead due to buffer usage, resulting to complicated placing and routing tasks and limiting the size of target circuit that can be implemented. We propose a simple algorithm that can efficiently realize timesharing of flip-flops by refining an initial partitioning. Experimental results show that implementation of our approach can eliminate all storage overhead while the resultant change in the amount of communication between sub-circuits can be kept less than /spl plusmn/4%. We have also designed and fabricated a new temporal communication module, and implemented our new approach on it.