Three-dimensional simulation of single electron transistors

We present a three-dimensional (3D) approach for the simulation of single electron transistor (SET) in which subregions with different types of confinement are present simultaneously. In particular, we have applied our model, based on the solution of the Schrodinger equation with DFT, to a split gate and a silicon on insulator (SOI) single electron transistor (SET). The solution of the Schrodinger equation with open boundary conditions has allowed us to compute the three-dimensional conductance in the linear response regime.