Enhanced high resistivity SOI wafers for RF applications

In this work, we investigate the impact of distinctly processed trap-rich layers of polysilicon inserted between BOX and HR Si substrate on the effective resistivity, substrate losses and crosstalk level in HR SOI wafers. The wafers were fabricated starting from p-type high resistivity bulk wafers with resistivity higher than 3 k/spl Omega/.cm. The wafers were first covered with a LPCVD layer of undoped polysilicon at 2 distinct temperatures (T/sub poly/=585 /spl deg/C, 625 /spl deg/C) and with varying thickness. This layer was afterwards passivated with a charge rich 3 /spl mu/m thick PECVD oxide of the reference wafer. The oxide layer was densified by RTA at 800 /spl deg/C during 20 s.