34.1 Gbps low jitter, low BER high-speed parallel CMOS interface for interconnections in high-speed memory test system

To solve the transmission bottleneck inside ATE systems, we developed a high-speed parallel CMOS interface macro, which is flexibly applicable to ASICs in ATE systems. The interface macro is capable of providing up to 16 TX and/or RX channels: Moreover, multiple macros can be implemented to one chip. The interface macro is capable of transmitting from DC to 34.1 Gbps (2.13 Gbps/spl times/16 channels). In order to achieve ultra-low BER, we have developed a low-jitter digital delay locked loop circuit as a 4-phase clock source for SerDes circuits. This solution yields 1.5 ps rms of random jitter. The random jitter of this macro is less than one-eighth of the interface using PLL. The eye-opening reaches 0.7UI at BER=10/sup -19/.