Hierarchical DFT methodology - a case study

A hierarchical approach to DFT is presented to address the issues encountered when inserting DFT into large SOC designs. There were challenges in implementing this methodology and the real motivation for implementation of a hierarchical DFT is to align with front-end and physical design process. Implementation of this method includes reduced runtime of tools and reduced pattern size. As a result of additional tester memory available using this technique, more testing was implemented. The case study uses a production design with sandburst, Inc (0.13 /spl mu/, 4 Mgate chip).