Design of a low power image watermarking encoder using dual voltage and frequency

In this paper, we propose a VLSI architecture and provide prototype implementation of a chip that can insert both invisible and visible watermarks in DCT domain. To our knowledge, this is the first ever low power watermarking chip having such watermarking functionalities. Various techniques, such as multiple voltages, multiple frequency, and clock gating are incorporated to reduce power consumption of the chip. The proposed architecture has a three stage pipeline structure and also uses parallelism to improve the overall performance. A prototype chip is designed and verified using various Cadence and Synopsys tools using TSMC 0.25 /spl mu/m technology. It runs at a dual frequency of 280 MHz and 70 MHz and at a dual voltage of 2.5 V and 1.5 V and contains 1.4 M transistors. The average power consumption of the chip is estimated to be 0.3 mW, which is five times less than its single supply voltage and single frequency operation.